I think it's to override the error code. We haveTom wrote: Wed Sep 24, 2025 1:17 pm It apparently increments a counter -- maybe the counter for the cycling valve's PWM signal? Looking at other KLR performance chips back in the day, it looks like maxing out the overboost table and clearing that counter (maybe to force the cycling valve to full boost?) was one of the ways they'd use.
0xf60 mov r1,#$33
0xf62 mov a,@r1
0xf63 jz $0F69
0xf65 add a,#$EF
0xf67 jnz $0F81
0xf69 mov a,r4
Location 33h contains the error code (if any). So if that's zero, we skip the next 2 instructions. At a glance it looks like those next 2 instructions check if the error code is something specific (i.e. whatever code would result in zero when added to 0xEF). For any other code, it skips to the end of the routine. This is probably how limp mode is implemented. Apparently there's one code that doesn't trigger it (not sure which one).
The Dinan bin file that I have replaces the conditional jz with
jmp $0769
(the address here is relative to the current bank so this can be read as 0xF69)
So it makes the CV PWM calculation ignore the error code.
